(a) Field of the Invention
The present invention relates to a radio frequency integrated circuit and a method for manufacturing the same. More particularly, the present invention relates to a radio frequency integrated circuit and a method for manufacturing the same in which leakage of current to a semiconductor substrate by radio frequency (RF) coupling is prevented such that a high quality factor is obtained.
(b) Description of the Related Art
The term xe2x80x9csemiconductorxe2x80x9d is very often taken to mean a semiconductor device manufactured with semiconducting materials, and semiconductor devices are classified into individual semiconductor elements and integrated circuits.
Individual semiconductor elements such as transistors, diodes, rectifiers and light converting elements (light emitting, light receiving elements) are devices made to perform specific functions in a circuit. By selecting a specific variety of semiconductor elements, an electronic circuit that executes a desired operation can be designed.
Further, with the integrated circuit, specific individual elements are provided in a single semiconductor chip to configure a circuit. There is continued development of radio frequency (RF) integrated circuits in recent times to increase the speed and reduce power consumption of semiconductor integrated circuits. The RF integrated circuit operates at radio frequencies of tens of cycles per second.
FIG. 1 shows a schematic sectional view of a conventional RF integrated circuit. It should be noted that a plurality of the elements to be described below are provided over an area of the integrated circuit.
In the conventional RF integrated circuit, a field oxide layer 2 is formed in a specific area of a semiconductor substrate 1 in order to form element separation areas, thereby defining active areas in the semiconductor substrate 1. A semiconductor element 3, which includes a gate G, a source S and a drain D, is formed in an active area of the semiconductor substrate 1. Also, a pre-metal dielectric (PMD) layer 4 is formed on the semiconductor element 3 and the field oxide layer 2. The PMD layer 4 electrically insulates the semiconductor substrate 1, which includes each element electrode of the semiconductor element 3, from a metal wiring layer. Also, a contact 5, for electrically connecting the element electrodes and the metal wiring layer, is formed in the PMD layer 4.
A first metal wiring layer 6 is formed on the PMD layer 4 and is connected to the contact 5. Further, an inter-metal dielectric (IMD) layer 7 is formed on the first metal wiring layer 6. The IMD layer 7 electrically insulates the first metal wiring layer 6 from an upper metal wiring layer. There is also included a via 8, which is formed in the IMD layer 7. The via 8 electrically connects the first metal wiring layer 6 to an upper metal wiring layer.
A second metal wiring layer 9, which is connected to the via 8, is formed on the IMD layer 7. Also, spiral coils 10 for forming inductors in the RF integrated circuit are provided in the second metal wiring layer 9 connecting specific vias 8. Finally, a capping layer 11 is formed on the second metal wiring layer 9.
In the conventional RF integrated circuit structured as in the above, a quality factor (Q), which is a multiple of a current flowing to both ends of an inductor (having an inductance L) of a spiral coil, is as shown in Equation 1 below.
Q=R/(wL)xe2x80x83xe2x80x83[Equation 1]
where w is 2xcfx80f, in which f is a frequency in resonance, and R is a resistance of a semiconductor substrate.
A value of the Q determined by Equation 1 is used as a target for a performance level of an inductor. Further, with reference to the graph of FIG. 2, which shows variations in characteristics of an inductor according to changes in resistance of a substrate, a value of the Q increase with increases in the resistance of a semiconductor substrate.
However, if there occurs current leakage (JRF in FIG. 1) as a result of RF coupling between the semiconductor substrate and an inductor, the value of the Q is negatively affected. To minimize a reduction in the value of the Q caused by current leakage, a high resistance GaAs substrate is used.
However, such high resistance GaAs substrates are costly and difficult to manufacture to large sizes, such as to an area of 8 square inches.
The present invention has been made in an effort to solve the above problems.
It is an object of the present invention to provide a radio frequency integrated circuit and a method for manufacturing the same, in which the integrated circuit can be easily manufactured to large sizes, and in which a high quality factor is obtained using a silicon wafer of a minimal unit price.
To achieve the above object, the present invention provides an RF integrated circuit and a method for manufacturing the same. The RF integrated circuit comprises an insulating layer including a plurality of windows; epitaxial silicon layers formed in a separated state on the insulating layer; semiconductor elements formed on the epitaxial silicon layers; a PMD layer formed on the epitaxial silicon layers and the insulating layer, and including contacts that connect electrode regions of the semiconductor elements; a first metal wiring layer formed on the PMD layer, and which forms circuit wiring by a metal film pattern connecting the contacts; an IMD layer formed on the first metal wiring layer, and including vias connecting portions of the first metal wiring layer; a second metal wiring layer formed on the IMD layer, and which forms circuit wiring by a thin film pattern connecting the vias; and a capping layer formed on the second metal wiring layer.
According to a feature of the present invention, the epitaxial silicon layer is formed on each the window.
According to another feature of the present invention, the second metal wiring layer includes spiral coils, which form inductors and connect specific vias.
The method comprises the steps of (a1) forming an insulating layer on a silicon wafer, and selectively etching the insulating layer to form a plurality of windows that expose the silicon wafer; (b1) forming an epitaxial silicon layer over an entire surface of the insulating layer by an epitaxial growth method using portions of the silicon wafer exposed through the windows, and planarized the epitaxial silicon layer; (c1) selectively etching the epitaxial silicon layer to realize a plurality of the epitaxial silicon layers, in which the epitaxial silicon layers of the each window region are separated; (d1) forming semiconductor elements on the epitaxial silicon layers; (e1) forming a PMD layer on the epitaxial silicon layers, and selectively etching the PMD layer to form contact holes for exposing portions of electrodes of the semiconductor elements; (f1) providing metal plugs in the contact holes, and forming and patterning a metal film to realize a first metal wiring layer; (g1) forming an IMD layer over the first metal wiring layer, and selectively etching the IMD layer such that portions of the first metal wiring layer are exposed to form via holes; (h1) providing metal plugs in the via holes to form vias, and forming and patterning a metal film on the IMD layer to form a second metal wiring layer; and (i1) forming a capping layer on the second metal wiring layer, and removing the silicon wafer.
According to a feature of the present invention, step (c1) is performed after the step (d1) of forming semiconductor elements on the epitaxial silicon layer.
According to another feature of the present invention, in step (a1), the insulatin layer is formed by CVD process.
According to yet another feature of the present invention, in step (b1), the epitaxial silicon layer is planarized by CMP.
According to still yet another feature of the present invention, in step (h1), spiral coils connecting specific vias are formed when the metal film on the IMD layer is patterned.
According to still yet another feature of the present invention, after step (i1) of removing the silicon wafer after forming the capping layer is formed on the second metal wiring layer, the capping layer is used as a support and a polishing process is performed on the silicon wafer to remove the silicon wafer.
According to still yet another feature of the present invention, a chemical mechanical polishing process is used as the polishing process.
According to still yet another feature of the present invention, the capping layer is formed to a thickness of between 50 and 100 xcexcm.